TTL NAND gate
In TTL device, each emitter acts as a diode, therefore, Q1 and 4kΩ resistor acts like a 2 -input AND gate. The rest of the circuit inverts the signal so that the over all circuits like a 2 input NAND gate. The output transistor (Q3 and Q4) form a totempole connection.
The input voltages A and B are either low (ideally grounded) or high (ideally grounded) or high (ideally grounded) or high (ideally +5V). If A or B is low, the base of Q1 is pulled down to approx 0.7 V. This reduces the base voltage of Q2 to almost zero. Therefore, Q2 cuts off with Q2 open, Q4 is off and the Q3 base is pulled high. The emitter of Q3 is only 0.7 V below the base and thus y output is pulled upto a high voltage.
On the other hand, when A and B are both high voltages, the emitter diodes of Q1 stop conducting and the collector diode goes into forward conduction. This forces Q2 to turn on. In turn, Q4 goes on and Q3 turns off producing a low output.
Adjoining table shows the input and output condition. Without diode D1 in the circuit, Q3 will conduct slightly when the output is low. To prevent this, the diode is instead, its voltage drop keeps the base emitter diode of Q3 reversed biased. In this way, only Q4 conducts when the output is low.