TTL NAND gate

In TTL device, each emitter acts as a diode, therefore, Q1 and 4kΩ resistor acts like a 2 -input AND gate. The rest of the circuit inverts the signal. The output transistor (Q3 and Q4) form a totempole connection.

The input voltages A and B are either low (ideally grounded) or high (ideally +5V). The base of Q1 is lowered to roughly 0.7 V if A or B are low. The base voltage of Q2 is virtually zero as a result. As a result, Q4 is off, Q3's base is pulled up, and Q2 cuts off with Q2 open. The output of Q3 is dragged up to a high voltage since the emitter is just 0.7 V below the base.

On the other hand, when A and B are both high voltages, the emitter diodes of Q1 stop conducting and the collector diode goes into forward conduction. This forces Q2 to turn on. In turn, Q4 goes on and Q3 turns off producing a low output.

Adjoining table shows the input and output condition. Without diode D1 in the circuit, Q3 will conduct slightly when the output is low. To prevent this, the diode is instead, its voltage drop keeps the base emitter diode of Q3 reversed biased. In this way, only Q4 conducts when the output is low.

This note is taken from MSC physics, Nepal.

This note is a part of the Physics Repository.