D flip flop (clocked)

The RS flipflop has two data inputs S and R. To store high bit (i.e. Q=1) S must be high (1) and to store low bit (i.e. Q=0), R must be high. The generation of two signal to drive flipflop is inconvenient. In many application, further the forbidden condition may occur. This drawbacks leads to the D flip flop. Above figure shows the construction and truth table of D flip flop.

When clock is low, the latch is disabled and D can change the value without affecting Q i.e Q remains in the last value (Qn). When clock is high the latch is enabled. Q is equal to value of D. When clock is again low, Q store the last value of D. D flip flop is modified form of RS flip flop.

Edge triggered D-flip flop

An edge triggered flip flop change the states either at positive edge (or rising edge or load edge) or at negative edge (falling edge or trailing edge) of the clock. Edge triggered flip flop is sensitive to its input only at the transition of the clock.

The clock provides train of square wave signals which are converted to spikes by RC circuit. The triggering occurs at positive going edge so it is called positive edge trigger

In the truth table when clock is low, D is 'don't care' and Q is in last state(Qn). When clock is high at positive edge, D appear on output Q and negative edge D is 'don't care' and Q stores the last state (Qn).