J k flip flop is popular and widely used flip flop. It's function is identical to RS flip flop except it has no forbidden case.

Set the flip flop

When J=1, K=1 it is possible to set or reset the flip flop. if Q is high, lower gate passes a reset signal on the next positive trigger. When Q is low, upper gate passes a set signal on next positive trigger. Thus Q changes to the complement of last state. So when J=1 or K=1, flip flop will toggle on the next positive trigger.

Racing in Jk flip flop

In Jk flip flop, when J and K are high, the flip flop switches to the opposite state called toggling. When the flip flop toggles more than once during a positive clock edge, it is called racing. Propagation delay prevents the JK flip flop from racing.

The above figure shows the logical diagram of JK flip flop. Here J and K are control input because they determine what the flip flop does when positive edge clock arrives. RC circuit converts rectangular waves into spikes. Because of AND gates the circuit is positive edge trigger.

When J=0 and K=0, AND gates are disabled then clock gets don't care condition and output remain in the last state.

During the positive edge of the clock, if J=0 and K=1, the upper gate is disabled. Hence, there is no way to set the flip flop. The only possibility is to reset it. When next positive clock arrives. lower gate passes a reset pulse. This makes the high Q low. So, when J=0 and K=1, next positive trigger of the clock reset the flip flop.

Explore

posts on Naya and its networks

Collections